In pre validation, it is also called as Design Under Verification, DUV in short. DUT is a term typically used in post validation of the silicon once the chip is fabricated.
#Modelsim testbench verilog verification#
Monitor the design input-output ports to capture design activityĬhecks output from the design with expected behaviorĬontains all the verification components mentioned aboveĬontains the environment that can be tweaked with different configuration settingsĭUT stands for Design Under Test and is the hardware design written in Verilog or VHDL. Generates different input stimulus to be driven to DUTĬontains design signals that can be driven or monitoredĭrives the generated stimulus to the design
![modelsim testbench verilog modelsim testbench verilog](https://i.stack.imgur.com/gUZFB.png)
Let's take a look at a simple testbench and try to understand about the various components that facilitate data transfer from and to the DUT. The example shown in Introduction is not modular, scalable, flexible or even re-usable because of the way DUT is connected, and how signals are driven.
![modelsim testbench verilog modelsim testbench verilog](https://www.nandland.com/vhdl/tutorials/images/tutorial-modelsim-beginner-6.png)
If a functional bug is found, then change the design to fix the bug.Check the output with expected behavior to find functional defects.Allow the design to process input and provide an output.Drive the design inputs with the generated stimulus.
![modelsim testbench verilog modelsim testbench verilog](https://res.cloudinary.com/df1s0wur2/image/upload/v1503807287/simEnv_owgbz6.png)